The present invention relates to a chip carrier, on which LSI chips are mounted, and in particular to a chip carrier suitable for a large scale information processing unit such as an electronic computer, etc., to which a high signal propagation velocity is required.
In order to drive LSI chips with a high reliability, it is necessary to seal the chips against external atmosphere to prevent the penetration of humidity, etc. For this reason a so-called chip carrier is widely used.
Further, with the intention of increasing the operation speed in an electronic computer, etc., it is necessary to package LSI chips having a high circuit density and many pins with a high density. Consequently it is desirable that the chip carriers, on which LSI chips are to be mounted, are also small and that a number of signal pins can be taken out therefrom, and further it is necessary to package a number of chip carriers on a multilayered wiring board. FIG. 6 shows an example of such a chip carrier, which is small and from which a number of pins can be taken out, which is proposed in JP-A No. 60-217649. In the figure reference numeral 1 is an LSI chip; 2 is a throughhole for in/outputting electric power and signals; 4 is a subboard; 7 is a cap; and 6' is a terminal pad. The terminal pads 6' are arranged two-dimensionally on the lower surface of the chip carrier.
On the other hand, with increasing circuit density of the LSI chip, the number of circuits, in which the logical state is switched simultaneously increases, which gives rise to a problem that so-called noise accompanying simultaneous switching is produced. In order to reduce this noise, it is common to mount e.g. a decoupling capacitor between a wire at the power source potential and a wire at the ground potential on the wiring board.
In this case, when the decoupling capacitor is mounted on the surface of the wiring board, it becomes necessary to extend the wiring from the capacitor to a point, where it is desired originally to connect the capacitor, which gives rise to a problem that the decoupling effect is reduced by the inductance of this connecting wire.
As a technique for solving the problematical point described above by reducing the length of the wire for connecting the capacitor, e.g. the followings are proposed. JP-A No. 58-111396 discloses a technique, by which a capacitor is located within the wiring board; JP-A No. 62-169461 shows an example, in which a capacitor is formed in a part of the package of a semiconductor device; and JP-A No. 61-247058 describes an example, by which a capacitor is incorporated in the upper portion (cap portion) of the chip carrier.